Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Scaricare il pdf (Pagina 50)

IP Core Configuration

III-38 Slave Controller – IP Core for Xilinx FPGAs

5.1.5 Process Data Interface tab

Several interfaces between ESC and the application are available:

 Digital I/O

 8 Bit asynchronous µController

 16 Bit asynchronous µController

 SPI slave

 PLB v4.6 on-chip bus

 OPB on-chip bus (deprecated, use only for legacy projects)

 General Purpose I/O

EtherCAT

Logic

PDI

SPI

Digital I/O

µC 8 Bit

PLB/

OPB

EtherCAT IP Core

Microblaze

RAM

…..

µC 16 BitPDI

FPGA

PHY

General

Purpose I/O

Figure 17: Available PDI Interfaces

The PDI can be selected from the pull down menu. After selection settings for the selected PDI are

shown and can be changed.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Pagina 50