Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Scaricare il pdf (Pagina 74)

IP Core Signals

III-62 Slave Controller – IP Core for Xilinx FPGAs

8.6.4.1 8 Bit µController Interface

Table 29 lists the signals used with an 8 Bit µC PDI.

Table 29: 8 Bit µC PDI

Condition

Name

Direction

Description

Tristate drivers inside

core (µController

configuration)

PDI_uC_DATA[7:0]

BIDIR

µC data bus

External tristate drivers

PDI_uC_DATA_IN[7:0]

INPUT

µC data bus:

µC  IP Core

PDI_uC_DATA_OUT[7:0]

OUTPUT

µC data bus :

IP Core  µC

8.6.4.2 16 Bit µController Interface

Table 30 lists the signals used with a 16 Bit µC PDI.

Table 30: 16 Bit µC PDI

Condition

Name

Direction

Description

Tristate drivers inside

core (µController

configuration)

PDI_uC_DATA[15:0]

BIDIR

µC data bus

External tristate drivers

PDI_uC_DATA_IN[15:0]

INPUT

µC data bus:

µC  IP Core

PDI_uC_DATA_OUT[15:0]

OUTPUT

µC data bus:

IP Core  µC

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 125 126

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