Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Manuale Utente Scaricare il pdf (Pagina 7)

CONTENTS

Slave Controller – IP Core for Altera FPGAs III-VII

10.2.9 SPI access errors and SPI status flag 97

10.2.10 2 Byte and 4 Byte SPI Masters 98

10.2.11 Timing specifications 99

10.3 Asynchronous 8/16 bit µController Interface 105

10.3.1 Interface 105

10.3.2 Configuration 105

10.3.3 µController access 106

10.3.4 Write access 106

10.3.5 Read access 106

10.3.6 µController access errors 107

10.3.7 Connection with 16 bit µControllers without byte addressing 107

10.3.8 Connection with 8 bit µControllers 108

10.3.9 Timing Specification 109

10.4 Avalon Slave Interface 113

10.4.1 Interface 113

10.4.2 Configuration 114

10.4.3 Interrupts 114

10.4.4 Data Bus With and SyncManager Configuration 114

10.4.5 Timing specifications 115

10.5 AXI3 On-Chip Bus 117

10.5.1 Interface 117

10.5.2 Configuration 119

10.5.3 Interrupts 119

10.5.4 Timing specifications 120

11 Distributed Clocks SYNC/LATCH Signals 122

11.1 Signals 122

11.2 Timing specifications 122

12 SII EEPROM Interface (I²C) 123

12.1 Signals 123

12.2 EEPROM Emulation 123

12.3 Timing specifications 123

13 Electrical Specifications 124

14 Synthesis Constraints 125

15 Appendix 129

15.1 Support and Service 129

15.1.1 Beckhoff’s branch offices and representatives 129

15.2 Beckhoff Headquarters 129

1 2 3 4 5 6 7 8 9 10 11 12 ... 140 141

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Beckhoff EtherCAT IP Core for Altera FPGAs v3.0.10 Manuale Utente Pagina 7