Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuale Utente Scaricare il pdf (Pagina 102)

Ethernet Interface

III-90 Slave Controller – IP Core for Xilinx FPGAs

9.4.4.1 TX_CLK Delay in PHY

Some PHYs offer RGMII-ID, which means, the TX_CLK is delayed internally in the PHY. The

EtherCAT IP Core itself cannot enable this feature using the MII management interface if the PHY

requires this. It is up to the IP Core user to enable this feature.

9.4.4.2 TX_CLK Delay on PCB

One option is to delay TX_CLK on the PCB.

9.4.4.3 TX_CLK Delay in FPGA with PLL

The delay of TX_CLK can be realized with a PLL providing a delayed CLK25 attached to the

CLK25_2NS input of the IP Core. This clock is used for the TX_CLK DDR output cell, while CLK25 is

used for the TX_CTL/TX_DATA DDR output cells.

9.4.4.4 TX_CLK Delay in FPGA without PLL

The delay of TX_CLK can be realized with routing delay inside the FPGA.

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v3.00k Manuale Utente Pagina 102