Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Scaricare il pdf (Pagina 114)

PDI Description

III-102 Slave Controller – IP Core for Xilinx FPGAs

10.4.3 Timing specifications

Table 56: PLB timing characteristics

Parameter

Min

Max

Comment

Clk

40 ns

PLB bus clock (f

Clk

≥25 MHz)

Read

a) 520 ns

b) 400 ns + 4*t

Clk

c) 460 ns + 3*t

Clk

a) 600 ns

b) 500 ns + 4*t

Clk

c) 620 ns + 4*t

Clk

32 Bit read access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

a) 360 ns

b) 240 ns + 4*t

Clk

c) 300 ns + 3*t

Clk

a) 440 ns

b) 340 ns + 4*t

Clk

c) 460 ns + 4*t

Clk

16 Bit read access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

a) 280 ns

b) 160 ns + 4*t

Clk

c) 220 ns + 3*t

Clk

a) 360 ns

b) 260 ns + 4*t

Clk

c) 380 ns + 4*t

Clk

8 Bit read access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

Write

a) 440 ns

b) 320 ns + 4*t

Clk

c) 400 ns + 3*t

Clk

a) 520 ns

b) 420 ns + 4*t

Clk

c) 560 ns + 4*t

Clk

32 Bit write access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

a) 280 ns

b) 160 ns + 4*t

Clk

c) 240 ns + 3*t

Clk

a) 360 ns

b) 260 ns + 4*t

Clk

c) 400 ns + 4*t

Clk

16 Bit write access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

a) 200 ns

b) 80 ns + 4*t

Clk

c) 160 ns + 3*t

Clk

a) 280 ns

b) 180 ns + 4*t

Clk

c) 320 ns + 4*t

Clk

8 Bit write access time

a) PLB_SPLB_CLK = 25 MHz

b) PLB_SPLB_CLK = N*25 MHz (N>1)

c) PLB_SPLB_CLK asynchronous

EtherCAT IP Core: time depends on synthesis results

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Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Pagina 114

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