Beckhoff EtherCAT IP Core for Xilinx FPGAs v2.04e Manuale Utente Scaricare il pdf (Pagina 23)

Features and Registers

Slave Controller – IP Core for Xilinx FPGAs III-11

2 Features and Registers

2.1 Features

Table 7: IP Core Feature Details

Feature

IP Core

Xilinx

®

V2.04e

IP Core

Xilinx

V2.04d

EtherCAT Ports

1-3

1-3

Permanent ports

1-3

1-3

Optional Bridge port 3

(EBUS or MII)

-

-

EBUS ports

-

-

MII ports

0-3

0-3

RMII ports

0-2

0-2

RGMII ports

-

-

Port 0

x

x

Ports 0, 1

x

x

Ports 0, 1, 2

x

x

EtherCAT mode

Direct

Direct

Slave Category

Full Slave

Full Slave

Position addressing

x

x

Node addressing

x

x

Logical addressing

x

x

Broadcast addressing

x

x

Physical Layer General

Features

FIFO Size configurable

(0x0100[18:16])

x

x

FIFO Size default from

SII EEPROM

x

x

Auto-Forwarder checks

CRC and SOF

x

x

Forwarded RX Error

indication, detection

and Counter

(0x0308:0x030B)

x

x

Lost Link Counter

(0x0310:0x0313)

c

c

Prevention of

circulating frames

x

x

Fallback: Port 0 opens

if all ports are closed

x

x

VLAN Tag and IP/UDP

support

x

x

Enhanced Link

Detection per port

configurable

x

x

General Ethernet Features

(MII/RMII/RGMII)

MII Management

Interface

(0x0510:0x051F)

c

c

Supported PHY

Address Offsets

any

any

Individual port PHY

addresses

-

-

Port PHY addresses

readable

-

-

Link Polarity

configurable

User logic

User logic

Enhanced Link

Detection supported

x

x

FX PHY support

(native)

-

-

PHY reset out signals

-

-

Link detection using

PHY signal (LED)

x

x

MI link status and

configuration

c

c

MI controllable by PDI

(0x0516:0x0517)

x

x

MI read error

(0x0510.13)

x

x

MI PHY configuration

update status

(0x0518.5)

x

x

Feature

IP Core

Xilinx

®

V2.04e

IP Core

Xilinx

V2.04d

MI preamble

suppression

x

x

Additional MCLK

x

x

Gigabit PHY

configuration

x

x

Gigabit PHY register 9

relaxed check

x

x

FX PHY configuration

-

-

Transparent Mode

-

-

MII Features

CLK25OUT as PHY

clock source

User logic

User logic

Bootstrap TX Shift

settings

c

c

Automatic TX Shift

setting (with TX_CLK)

c

c

TX Shift not necessary

(PHY TX_CLK as clock

source)

-

-

FIFO size reduction

steps

1

1

PDI General Features

Increased PDI

performance

-

-

Extended PDI

Configuration

(0x0152:0x0153)

x

x

PDI Error Counter

(0x030D)

c

c

PDI Error Code

(0x030E)

c

c

CPU_CLK output (10,

20, 25 MHz)

User logic

User logic

SOF, EOF, WD_TRIG

and WD_STATE

independent of PDI

x

x

Available PDIs and PDI

features depending on

port configuration

-

-

PDI selection at run-

time (SII EEPROM)

-

-

PDI active immediately

(SII EEPROM settings

ignored)

x

x

PDI function

acknowledge by write

-

-

PDI Information

register

0x014E:0x014F

-

-

Digital I/O PDI

x

x

Digital I/O width [bits]

8/16/24/32

8/16/24/32

PDI Control register

value (0x0140:0x0141)

4

4

Control/Status signals:

7

7

LATCH_IN

x

x

SOF

x

x

OUTVALID

x

x

WD_TRIG

x

x

OE_CONF

-

-

OE_EXT

x

x

EEPROM_

Loaded

-

-

WD_STATE

x

x

EOF

x

x

Granularity of direction

configuration [bits]

8

8

Bidirectional mode

- (User

logic)

- (User

logic)

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 125 126

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