
Features and Registers
Slave Controller – IP Core for Xilinx FPGAs III-15
2.2 Registers
An EtherCAT Slave Controller (ESC) has an address space of 64KByte. The first block of 4KByte
(0x0000:0x0FFF) is dedicated for registers. The process data RAM starts at address 0x1000, its size
is configurable.
Some registers are implemented depending on the configuration.
Table 9 gives an overview of the available registers.
Table 9: Register availability
V2.4.0-V2.4.4/
V2.04a-V2.04e
Register set
S M L
V2.3.0-V2.3.2/
V2.03a-V2.03d
Register set
S M L
V2.2.1/V2.2.0/
V2.02a
Register set
S M L
Configured Station
Address
Write Register
Protection
Physical Read/Write
Offset
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